20 ns, the counting value is 2^12, counting time period is: For instances if the test clock is 50 MHz, i.e. The reference clock counts for a fixed number clock cycles. The basic idea is reported in the figure Figure2 – Clock counter architectureĪs you can see, we use a reference clock to detect a test clock. So let’s see how to implement a clock frequency counter. The first solution maybe didn’t need a blog post or further explanation If we need to verify the clock frequency, we can How can you measure the clock frequency? You can guess something from the blinking rate but is only a rough estimation.Ĭlick Here to enroll the free course “How To Measure Clock Frequency in FPGA” Doing this you can monitor if your clock is present. I mean, connect the clock to a module that implements a counter to generate a slow signal that can drive a LED for instance at the toggling rate of one second. if you divide the clock rate to a “human” frequency you can use it to blink a LED. The clock is a periodic signal changing very fast, so you cannot directly connect to a LED but…. Well, if you did simulate your VHDL design, and you did respect the golden rules for a digital design ( you can find some example and the available courses here) external reset and clock are often the main issues of your design!įor the reset pin, the solution is very simple: you can map reset to an output pin connected to a LED so you can check if the reset signal is working fine… Maybe you are thinking… it is not possible that the main errors are the clock and reset!

the clock signal is absent or of a wrong value.

There is also a good news… If you did a good simulation of your digital design, often the problems you get during the test on a board are of the same type: I have a bad news when you start to debug your design on FPGA it always doesn’t work… Did it happen to you? Figure1 – clock signal example If you implement a (good) synchronous design and simulate it, you are very confident that the design can work as it should. When you start the debug of your VHDL layout code on FPGA, often your design doesn’t work as it should!ĭigital design has a big advantage w.r.t analog design: When you use an FPGA you always need a clock.

Convert clock speed to cycle time